Timing Designer Tool

Spartan Start board
FPGA 개발 보드
Accessory

TempPoint
Data Translation

Step1. DSP System Modeling - Using familiar tools like MATLAB and Simulink, users develop models of their DSP systems. System Generator includes a Xilinx blockset that comprises basic level building blocks like FFTs, and advanced DSP algorithms like digital down converters.
Users can also bring in their own HDL Modules via HDL co-simulation, or write MATLAB code for combinational control logic or statemachine.

Step2. System Generation - System Generation for DSP is invoked from Simulink through the System Generator for DSP token. Pushing the "Generate" button generates VHDL and cores for all the Xilinx Blocks on the sheet containing the token, and on any sheets beneath it in the design hierarchy. FPGA designs are generated using Xilinx optimized LogiCOREs, ensuring that the most efficient implementation is being produced.

Step3. HDL Synthesis - Once VHDL has been generated by System Generator for DSP, users may want to synthesize this for optimal FPGA implementations whether it be for high performance or optimal area. Users can choose from one of three popular synthesis engines including Xilinx's own XST, Synplify Pro from Synplicity and FPGA Advantage from Mentor Graphics.

Step4. Simulation/Verification - A VHDL testbench and data vectors can also be created by System Generator for DSP. These vectors represent the inputs and expected outputs seen in the Simulink simulation, and allow the designer to easily see any discrepancies between the Simulink and VHDL simulation results. FPGA Advantage can be used to conduct simulations of DSP systems prior to implementation. If doing HDL co-simulation, ModelSim is required.

Step5. FPGA Implementation - Finally, designers use the industry's best ISE implementation tools to place route and verify the design in a Xilinx FPGA.

Step6. In-System Debug - Use the Hardware co-simulation capability to accelerate simulation and verify your design in hardware. Including ChipScope Pro to your design flow will alow real-time debugging at system speed.